module project_instructionmemory (iClk, MemWrite, Address, WriteData, ReadData);

input iClk,MemWrite;
input [5:0]Address;
input [31:0] WriteData;
output [31:0] ReadData;

reg [31:0] RAM[63:0];

initial begin
RAM[0][31:0]=00110100001000000000000000000001;// t0=R1
RAM[1][31:0]=00110100011000000000000000010001;
RAM[2][31:0]=00110100100000000000000000000001;
RAM[3][31:0]=10101100001000010000000000000000;
RAM[4][31:0]=10000000011001000000100000000000;
RAM[5][31:0]=00010000010000010000000000000001;
RAM[6][31:0]=00001000000000000000000000000011;
RAM[7][31:0]=00110100100000000000000000000000;
RAM[8][31:0]=00110100001000000000000000000001;
RAM[9][31:0]=10000000100000010010000000000000;
RAM[10][31:0]=00001000010000110000100000000000;
RAM[11][31:0]=00010000010000010000000000000001;
RAM[12][31:0]=00001000000000000000000000001001;
RAM[13][31:0]=10101100001001000000000000000000;
RAM[63:14]{31:0}=0;
end

assign ReadData=Ram[Address[5:0]];

always @(posedge iClk) begin
if(MemWrite)
	RAM[Address[5:0]]<=WriteData;
end

endmodule
